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ATmega128
Timer/Counter
Clock Sources
Counter Unit
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the clock select logic which is controlled by the Clock Select (CSn2:0) bits located
in the Timer/Counter Control Register B (TCCRnB). For details on clock sources and prescaler,
see “Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers” on page 143 .
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 47 shows a block diagram of the counter and its surroundings.
Figure 47. Counter Unit Block Diagram
DATA BUS (8-bit)
TOVn
(Int.Req.)
TEMP (8-bit)
Clock Select
TCNTnH (8-bit) TCNTnL (8-bit)
TCNTn (16-bit Counter)
Count
Clear
Direction
Control Logic
clk Tn
Edge
Detector
Tn
( From Prescaler )
Signal description (internal signals):
TOP
BOTTOM
Count
Direction
Clear
clk T n
TOP
BOTTOM
Increment or decrement TCNTn by 1.
Select between increment and decrement.
Clear TCNTn (set all bits to zero).
Timer/Counter clock.
Signalize that TCNTn has reached maximum value.
Signalize that TCNTn has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con-
taining the upper 8-bits of the counter, and Counter Low (TCNTnL) containing the lower 8-bits.
The TCNTnH Register can only be indirectly accessed by the CPU. W hen the CPU does an
access to the TCNTnH I/O location, the CPU accesses the high byte Temporary Register
(TEMP). The Temporary Register is updated with the TCNTnH value when the TCNTnL is read,
and TCNTnH is updated with the Temporary Register value when TCNTnL is written. This
allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit
data bus. It is important to notice that there are special cases of writing to the TCNTn Register
when the counter is counting that will give unpredictable results. The special cases are
described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each Timer Clock (clk T n ). The clk T n can be generated from an external or internal clock
source, selected by the Clock Select bits (CSn2:0). W hen no clock source is selected (CSn2:0 =
0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, independent
of whether clk T n is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
( W GMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB).
There are close connections between how the counter behaves (counts) and how waveforms
117
2467X–AVR–06/11
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